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 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LV048A/PI90LVT048A
3V LVDS Quad Flow-Through Differential Line Receivers
Features
* * * * * * * * * * * * * * * 500 Mbps (250 MHz) switching rates Flow-through pinout simplifies PCB layout 150ps channel-to-channel skew (typical) 100ps differential skew (typical) 2.7ns maximum propagation delay 3.3V power supply design High impedance LVDS inputs on power down Low Power design (40mW, 3.3V static) Wide common-mode input voltage range: 0.2V to 2.7V Accepts small swing (350mV typical) differential signal levels Supports open, short and terminated input fail-safe Low-power state when in fail-safe Conforms to ANSI/TIA/EIA-644 Standard Industrial temperature operating range (-40C to +85C) Packaging (Pb-free & Green available): - 16-pin SOIC (W) - 16-pin TSSOP (L)
Description
The PI90LV048A/PI90LVT048A quad flow-through differential line receivers are designed for applications requiring ultra low-power dissipation and high data rates. The device is designed to support data rates in excess of 500 Mbps (250 MHz) using Low Voltage Differential Signaling (LVDS) technology. The devices accept low-voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver supports a 3-state function, which may be used to multiplex outputs, and also supports open, shorted and terminated (100-ohms) input failsafe. The receiver output will be HIGH for all fail-safe conditions. PI90LVT048A features integrated parallel termination resistors (nominally 110-ohms) that eliminate the requirement for four discrete termination resistors and reduce stud length. PI90LV048A inputs are high impedance and require an external termination resistor when used in a point-to-point connection. The devices have a flow-through pinout for easy PCB layout. The EN and EN inputs are ANDed together and control the 3-state outputs. The enables are common to all four receivers. The PI90LV048A and companion LVDS line driver (eg. PI90LV047A) provide a new alternative to high-power PECL/ECL devices for high-speed point-to-point interface applications.
Block Diagram
4 Places PI90LVT048A Only
RIN1+
100
R1
ROUT1
RIN1- RIN2+ R2 RIN2-
Pin Configuration
ROUT2
RIN1-
RIN3+ R3 RIN3- RIN4+ R4 RIN4- ROUT3
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
EN ROUT1 ROUT2 VCC GND ROUT3 ROUT4 EN
RIN1+ RIN2+ RIN2-
ROUT4
RIN3- RIN3+ RIN4+
EN EN
RIN4-
Truth Table
Enable s EN H EN L or Open Inputs RIN+ - RIN- VID 0.1V VID -0.1V Full fail- safe OPEN/SHORT or terminated All other combinations of ENABLE inputs
1
Outputs ROUT H L H Z
PS8608A 10/04/04
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PI90LV048A/PI90LVT048A 3V LVDS Quad Flow-Through Differential Line Receivers
Supply Voltage (VCC) .............................................. -0.3V to +4V Input Voltage (RIN+ - RIN-) ................................. -0.3V to 3.9V) Enable Input Voltage (EN, EN) .................. -0.3V to (VCC + 0.3V) Output Voltage (ROUT) ............................. -0.3V to (VCC + 0.3V) Maximum Package Power Dissipation: +25C M Package ................................................................. 1088 mW MTC Package ............................................................... 866 mW Derate M Package .............................. 8.5 mW/C above +25C Derate MTC Package ........................ 6.9 mW/C above +25C Storage Temperature Range .............................. -65C to +150C
Absolute Maximum Ratings
Lead Temperature Range Soldering (4 seconds) ................................................... +260C Maximum Junction Temperature ...................................... +150C ESD Rating(10) (HBM, 1.5kW, 100pF) ...................................................... 10kV (EIAJ, 0W, 200pF) ......................................................... 1200V
Recommended Operating Conditions
Min Typ Supply Voltage (VCC) +3.0 +3.3 Receiver Input Voltage GND Operating Free Air Temperature (TA) -40 +25 Max Units +3.6 V +3.0 V +85 C
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified(2, 3).
Symbol VTH VTL VCMR IIN Parame te r Differential input high treshold Differential input lowtreshold Common- mode voltage range Input Current Te s t Conditions VC M = +1.2V, 0.05V, 2.95V(1 3 ) VID = 200mV peak- to- peak(5 ) VIN = +2.8V VIN = 0V VIN = +3.6V VO H VO L IO S IO Z VIH VIL II VC L IC C IC C Z RTER M CW Output High Voltage Output low voltage Output short circuit current Output 3- State current Input high voltage Input low voltage Input current Input clamp voltage No load supply current Receivers enabled No load supply current Receivers disabled Termination input resistance (PI90LVT048A) Input capacitance VIN = 0V or VC C , Other Input = VC C or GND IC L = -18mA EN= VCC, One Differential Input = VCC other Differential Input = GND EN= GND, One Differential Input = VCC other Differential Input = GND VIN = VC C or 0 EN, EN VC C = 3.6V or 0V VC C = 0V RIN + , RIN - Pin M in. -100 0.1 -10 -10 -20 2.7 2.7 RO U T 2.7 -15 -10 2.0 GND -20 -1.5 5 -0.8 9 VC C 1 90 110 5 5 132 10 pF 15 mA 5 1 1 3.3 3.3 3.3 0.05 -47 1 0.25 -100 +10 VC C 0.8 +20 mA A V A V V 2.6 +10 +10 +20 A Typ. M ax. Units +100 mV V
IO H = -0.4mA, VID = +200mV IO H = -0.4mA, Input terminated IO H = -0.4mA, Input shorted IO L = 2mA, VID = -200mV Enabled, VO U T = 0V(11 ) Disabled, VO U T = 0V or VC C
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PS8608A
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PI90LV048A/PI90LVT048A 3V LVDS Quad Flow-Through Differential Line Receivers
Switching Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.(2,3)
Symbol tP HLD tP LHD tS K D1 tS K D2 tS K D3 tS K D4 tTLH tTHL tP HZ tP LZ tP ZH tP ZL fM AX
Parame te r Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew, tPHLD - tPLHD Channel- to- Channel Skew(7) Differential Part- to- Part Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency(14) Skew(8) Differential Part- to- Part Skew(9) ( 6 )
Conditions CL = 15pF VID = 200mV (Figures 1 & 2)
M in. 1.2 1. 2 0 0
Typ. 2.0 1. 9 0.1 0.15
M ax. 3.2 3.2 0.4 0.5 1. 0 1. 5
Units
0.5 0.35 RL = 2 kohms, CL = 15pF (Figures 3 & 4) 8 8 9 9 All Channels switching 250
1. 0 1.0 14 15 14 14
ns
MHz
Notes 1. "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation. 2. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified. 3. All typicals are given for: VCC = +3.3V, TA = +25C. 4. Generator waveform for all tests unless otherwise specified: f =1 MHz, ZO =50 ohms, tr and tf (0% to 100%) 3ns for RIN. 5. The VCMR range is reduced for larger VID. Example: if VID = 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs shorted is not supported over the common-mode range of 0V to 2.4V, but is supported only with inputs shorted and no external commonmode voltage applied. A VID up to VCC - 0V may be applied to the RIN+ /RIN- inputs with the Common-Mode voltage set to VCC/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200mV to 400mV. Skew specifications apply for 200mV VID 800mV over the common-mode range . 6. tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel 7. tSKD2, Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. 8. tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC, and within 5C of each other within the operating temperature range. 9. tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max-Min| differential propagation delay. 10. ESD Ratings: HBM (1.5 kohms, 100pF) 10kV EIAJ (0 ohm, 200pF) 1200V 11. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. 12. CL includes probe and jig capacitance. 13. VCC is always higher than RIN+ and RIN- voltage. RIN- and RIN+ are allowed to have a voltage range -0.2V to VCC - V ID/2. However, to be compliant with AC specifications, the common voltage range is 0.1V to 2.3V 14 f MAX generator input conditions: t r = t f <1ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35V peak to peak). Output criteria: 60/40% duty cycle, VOL (max 0.4V), VOH (min 2.7V), Load = 15pF (stray plus probes).
3
PS8608A
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PI90LV048A/PI90LVT048A 3V LVDS Quad Flow-Through Differential Line Receivers
Parameter Measurement Information
RIN+ Generator 50 RIN- 50 Receiver Enabled R CL ROUT
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
RIN- 0V Differential RIN+ tPLHD 80% ROUT 20% tTLH 1.5V VDIFF = DOUT+ - DOUT- 20% 80% 1.5V tPHLD VID = 200mV 1.2V
+1.3V +1.1V VOH
VOL tTHL
Figure 2. DriverPropagation Delay & Transition Time Waveforms
S1 VCC
RIN+ EN Generator 50 EN 1/4 PI90LV048A RIN-
RL Device Under Test CL ROUT
CL includes load and test jig capacitance. S1 = VCC for tPZL and tPLZ measurements. S1 = GND for tPZH and tPHZ measurements.
Figure 3. Receiver 3-State Delay Test Circuit
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PS8608A
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PI90LV048A/PI90LVT048A 3V LVDS Quad Flow-Through Differential Line Receivers
Parameter Measurement Information (continued)
EN When EN = GND or OPEN 1.5V 1.5V 0V 3V 1.5V EN When EN = VCC tPLZ tPZL VCC 50% Output When VID = -100mV tPHZ Output When VID = +100mV 0.5V 50% GND 0.5V tPZH VOL VOH 1.5V 0V 3V
Figure 4. Receiver 3-State Delay Waveforms
Typical Application
Enable 1/4 PI90LV048A
+
Data Input 1/4 PI90LV047A
RT
100
-
Data Output
Figure 5. Point-to-Point Application
5
PS8608A
10/04/04
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PI90LV048A/PI90LVT048A 3V LVDS Quad Flow-Through Differential Line Receivers
Packaging Mechanical: 16-Pin SOIC (W)
16
.149 .157
3.78 3.99 .0099 .0196 0.25 x 45 0.50
1 .386 .393 9.80 10.00 .0155 .0260 0.393 0.660 REF .053 .068 1.35 1.75 SEATING PLANE 0-8 0.41 1.27 .016 .050 .0075 .0098 0.19 0.25
.2284 .2440 5.80 6.20
.050 BSC 1.27
.013 .020 0.330 0.508
.0040 0.10 .0098 0.25
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
Packaging Mechanical: 16-Pin TSSOP (L)
16
.169 .177
4.3 4.5
1 .193 .201 4.9 5.1 .004 .008 .047 max. 1.20 SEATING PLANE 0.45 .018 0.75 .030 .252 BSC 6.4
0.09 0.20
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 .006
0.05 0.15 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS
6
PS8608A
10/04/04
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LV048A/PI90LVT048A 3V LVDS Quad Flow-Through Differential Line Receivers
Ordering Information
Ordering Code PI90LV048AW PI90LV048AWE PI90LV048AL PI90LV048ALE PI90LVT048AW PI90LVT048AWE PI90LVT048AL PI90LVT048ALE Package Code W W L L W W L L Package Type 16-pin SOIC Pb-free & Green, 16-pin SOIC 16-pin TSSOP Pb-free & Green, 16-pin TSSOP 16-pin SOIC Pb-free & Green, 16-pin SOIC 16-pin TSSOP Pb-free & Green, 16-pin TSSOP
Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. X = Tape and reel
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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PS8608A 10/04/04


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